DS070 (v2.1) June 1, 2000 www.xilinx.com 1
Product Specification 1-800-255-7778
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer List ing.)
• Also av ailable under the following Standard Microcircuit
Drawings (SMD ): 5962-94717 and 5962-95617.
• Configuration one-time prog rammabl e (O TP) read-only
memory designed to store configuration bitstreams of
Xilinx FP GA device s
• On-chip address count er, increment ed by ea ch rising
edge on the clock inpu t
• Simple interf ace to the FPGA requires only one user
I/O p i n
• Cascadable for storing longer or multiple bitstreams
• Programmable reset pola rity (active High or active
Low) for compatibility with different FPG A solutions
• Lo w-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Found ation ser ies software packages.
Description
The XC1700D QPRO™ f amily of configuration PROMs pro-
vide an easy-to-use, cost-effect ive method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FP GA generate s the ap propri ate number of clock pulses to
complete the configuration. Once configured, it disabl es the
PROM. When the FPGA is in Slav e Serial mode, the PROM
and the FPGA must both be clock ed by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other memb ers of the family.
For device program ming, either the Xilinx Al liance™ or the
Foundation™ series development systems compiles the
FP GA design f ile into a st andard HE X format wh ich is then
transferred to most commercial PROM programmers.
QPRO Family of XC1 700D QML
Configuration PROMs
DS070 (v2.1) June 1, 2000 Pr oduct S pecifi cat i on
R
Figure 1: S im p lif ie d B lo ck Diag ram (d oes not show prog ra m m i ng ci rcuit)
EPROM
Cell
Matrix
Address Counter
CE
DATA
OE
Output
CLK
V
CC
V
PP
GND
DS027_01_021500
TC
OE
RESET/
OE/
RESET
or
CEO
