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DS069

DS069首页预览图
型号: DS069
PDF文件:
  • DS069 PDF文件
  • DS069 PDF在线浏览
功能描述: 15 ns pin-to-pin logic delays on all pins
PDF文件大小: 120.93 Kbytes
PDF页数: 共12页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS069
PDF页面索引
120%
DS069 (v5.0) May 17, 2013 www.xilinx.com
Product Specification 1
© 1998–2006, 2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Product Obsolete/Under Obsolescence
Features
15 ns pin-to-pin logic delays on all pins
•f
CNT
to 95 MHz
288 macrocells with 6,400 usable gates
Up to 166 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available 352-pin BGA and 208-pin HQFP packages
Description
The XC95288 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 15 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95288 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95288
device.
0
XC95288 In-System
Programmable CPLD
DS069 (v5.0) May 17, 2013
05
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XC95288
Clock Frequency (MHz)
Typical I
CC
(mA)
050
300
(500)
(700)
(500)
600
900
100
High Performance
Low Power
DS069_01_110101
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