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DS067

DS067首页预览图
型号: DS067
PDF文件:
  • DS067 PDF文件
  • DS067 PDF在线浏览
功能描述: Enhanced pin-locking architecture
PDF文件大小: 277.55 Kbytes
PDF页数: 共10页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS067
PDF页面索引
120%
DS067 (v5.7) May 28, 2009 www.xilinx.com
Product Specification 1
© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
All other trademarks are the property of their respective owners.
Features
7.5 ns pin-to-pin logic delays on all pins
•f
CNT
to 111 MHz
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block (FB)
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144
device.
0
XC95144 In-System
Programmable CPLD
DS067 (v5.7) May 28, 2009
05
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XC95144
Clock Frequency (MHz)
Typical I
CC
(mA)
050
200
(480)
(320)
400
600
100
High Performance
Low Power
DS067_01_110101
(160)
(300)
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