• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • DS064 PDF文件及第1页内容在线浏览

DS064

DS064首页预览图
型号: DS064
PDF文件:
  • DS064 PDF文件
  • DS064 PDF在线浏览
功能描述: 5 ns pin-to-pin logic delays on all pins
PDF文件大小: 121.92 Kbytes
PDF页数: 共8页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS064
供应商
型号
品牌
封装
批号
库存数量
备注
询价
  • 深圳诚思涵科技有限公司

    9

    0755-23947236/8301550615302723671/15820783671曾小姐0755-82815131深圳市福田区华强北路上步工业区101栋518室11011880

  • DS0644
  •  
  • 2019+ 
  •  
  • 20000 
  • 进口原装现货一级代理商! 

PDF页面索引
120%
DS064 (v7.0) May 17, 2013 www.xilinx.com 1
Product Specification
© 1998, 2003-2006, 2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
– PRODUCT OBSOLETE / UNDER OBSOLESCENCE –
Features
5 ns pin-to-pin logic delays on all pins
•f
CNT
to 100 MHz
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 44-pin VQFP, 48-pin CSP
packages
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture
overview.
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
0
XC9536 In-System
Programmable CPLD
DS064 (v7.0) May 17, 2013
05
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency for XC9536
Clock Frequency (MHz)
Typical I
CC
(mA)
050
(50)
(30)
(83)
(50)
100
High Performance
Low Power
DS064_01_110101
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价