DS063 (v5.1) September 22, 2003 www.xilinx.com 1
Product Specification 1-800-255-7778
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Features
• High-perform anc e
- 5 ns pin-to-pin logic delays on all pins
-f
CNT
to 125 MHz
• Large density range
- 36 to 288 macr ocells with 800 to 6,400 usable
gates
• 5V in-system programmable
- E ndurance of 10,000 program/erase cycles
- Prog ram/erase ov er full commercial v oltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Glo bal and product term clocks, outp ut enables,
set and reset signals
- Extensive IEEE Std 1149.1 boundar y -scan (JTAG)
support
- P rogrammable power reduction mod e in each
macrocel l
- Slew rate control on individual outputs
- User programmable ground pin capability
- E xtende d patter n secu rity featu res for design
protection
- High-drive 24 mA outp uts
- 3 .3V or 5 V I/O cap abilit y
- A dvanced CMOS 5V Fast FLAS H™ t echnology
- Supports parallel programmi ng of multiple XC9500
devices
Family Overview
The XC9500 CPLD family provides advanced in-system
programming and test capabilities for high performance,
genera l pur pose logi c integration. All devices are in-system
programmable for a minimum of 10,000 program/erase
cycles. E xte nsive IEEE 1149.1 (JTAG) boun dary-scan sup-
port is also included on all family membe rs.
As shown in Table 1, logic density of the XC9500 devices
ranges from 800 to over 6,400 usable gates with 36 to 288
registers, respectively. Multiple package options a nd asso-
ciated I/O c apacity a re shown in Table 2. The XC95 00 fam-
ily is fully pin-compatible allowing easy design migration
across multiple density opti ons in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outpu ts provide 24 mA drive.
0
XC9500 In-System Programm able
CPLD Family
DS063 (v5.1) September 22, 2003
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Pr oduct S pecifica tio n
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Table 1: XC9500 Device Family
XC9536 XC9572 XC95108 XC95144 XC95216 XC95288
Macrocel ls 36 72 108 144 216 288
Usable Gates 800 1,600 2,400 3, 200 4,800 6,400
Registers 36 72 108 144 216 288
T
PD
(ns) 5 7.5 7.5 7.5 10 15
T
SU
(ns) 3.5 4.5 4.5 4.5 6.0 8.0
T
CO
(n s) 4.0 4.5 4.5 4.5 6.0 8.0
f
CNT
(MHz)
(1)
100 125 125 125 111.1 92.2
f
SYSTEM
(MHz)
(2)
100 83.3 83.3 83.3 66.7 56.6
Notes:
1. f
CNT
= Operating freque ncy for 16-bit counters .
2. f
SYSTEM
= I nternal operating frequency for general purpose system designs spanning multiple FBs.
