DS050 (v2.2) August 27, 2001 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 288 macrocells with 6,400 usable gates
• Available in small footpri nt packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
• Opti mized for high-performance 2.5V systems
- Low power operation
- Multi-voltage operation
• Advanced syste m featu re s
- In-system programm able
- Four separa te output banks
- Superior pin-loc kin g and routability with
FastCONNECT II™ switch matrix
- Extr a wide 54-input Function Blocks
- Up to 90 product-ter m s per macrocell with
individual product-ter m allocation
- Local clock inversion with three glob al and one
product-term clock s
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- B us-hold cirui tr y on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- E SD protection exc eedi ng 2,00 0V
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 5 ns.
Power Estima tion
Power dissipation in CPLDs can vary subs tantially dep end-
ing on the system f requency, design appl ication and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
F or a general estimate of I
CC
, the follo wing equation may be
used:
I
CC
(m A) =
MC
HP
(0.36) + MC
LP
(0.23) + MC(0.005 mA/MHz) f
W here:
MC
HP
= Macrocells in high-perfo rm ance (default) mode
MC
LP
= Macrocells in low-power mode
MC = Total numbe r of macrocell s used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
CC
value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
0
XC 95288X V High-Performance
CPLD
DS050 (v2.2) August 27, 2001
05
Advance Product Specification
R
Figure 1: Typical I
CC
vs. Freque ncy for XC95288XV
Clock Frequency (MHz)
Typical I
CC
(mA)
100 200 250
DS050_01_012501
200
250
300
350
400
450
50
50 150
150
100
0
120 MHz
H
i
gh P
e
r
form
a
nce
200 MHz
Low Powe
r
