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DS049

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型号: DS049
PDF文件:
  • DS049 PDF文件
  • DS049 PDF在线浏览
功能描述: High-Performance CPLD
PDF文件大小: 212.12 Kbytes
PDF页数: 共19页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS049
PDF页面索引
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DS049 (v3.0) June 25, 2007 www.xilinx.com 1
Product Specification
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Note: This product is being discontinued. You cannot
order parts in this family after May 14, 2008. Xilinx recom-
mends replacing XC9500XV devices with equivalent
XC9500XL devices in all designs as soon as possible. Rec-
ommended replacements are pin compatible, however
require a V
CC
change to 3.3V, and a recompile of the design
file. In addition, there is no 1.8V I/O support, and for the 144
and 288 macrocell devices only one output bank is sup-
ported. See XCN07010
for de ta ils reg ardin g this d iscont inu-
ation, including device replacement recomendations for the
XC9500XV device family.
Features
Optimized for high-performance 2.5V systems
- 5 ns pin-to-pin logic delays
- Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
- Lower power operation
- Multi-voltage operation
- FastFLASH technology
Advanced system features
- In-system programmable
- Output banking (XC95144XV, XC95288XV)
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
support on all devices
Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable
gates
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 3.3V core XC9500XL family in
common package footprints
Hot Plugging capability
Family Overview
The XC9500XV family is a 2.5V CPLD family targeted for
high-performance, low-voltage applications in leading-edge
communications and computing systems, where high
device reliability and low power dissipation is important.
Each XC9500XV device supports in-system programming
(ISP) and the full IEEE 1149.1 (JTAG) boundary-scan,
allowing superior debug and design iteration capability for
small form-factor packages. The XC9500XV family is
designed to work closely with the Xilinx Spartan™-XL and
Virtex™ FPGA families, allowing system designers to parti-
tion logic optimally between fast interface circuitry and
high-density general purpose logic. As shown in Table 1,
logic densi ty o f the XC9500 XV d evic es ran ges from 80 0 t o
6400 usable gates with 36 to 288 registers, respectively.
Multiple package options and associated I/O capacity are
shown in Table 2. The XC9500X V fam il y membe r s ar e fully
pin-compatible, allowing easy design migration across mul-
tiple density options in a given package footprint.
The XC9500XV architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming thr oughou t the f ull com merc ial oper ating r ange a nd a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retentio n supp orts longer and m ore rel iabl e system operat-
ing life.
Adva nced sys tem featur es includ e output s lew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 3.3V and 2.5V
inputs, and the outputs may be configured for 3.3V, 2.5V, or
1.8V operation. The XC9500XV device exhibits symmetric
full 2.5V output voltage swing to allow balanced rise and fall
times.
Architecture Description
Each XC9500XV device is a subsystem consisting of multi-
ple F unc tio n Bl ocks (FB s) and I /O B lo cks ( IO Bs) f ull y i nter-
connected by the Fast CONNECT II switch matrix. The IOB
0
XC9500XV Family
High-Performance CPLD
DS049 (v3.0 ) June 25, 2007
06
Product Specification
R
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