APPLICATION NOTE
DS 042 (v1.3) October 9, 2000 www.xilinx.com 1
1-800-255-7778
This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.
Features
• Industry's first TotalCMOS™ PLD - both CMOS design
and pr o ce s s t ec hn o log ies
• Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
• 5V, In-Syste m Programma ble (IS P) using a JTAG
interface
- O n-chi p supe r v ol tag e ge ne ration
- ISP commands include: Enable, Erase, Program,
Verify
- Supported by mu ltiple ISP pr ogramming platfo rms
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- JT AG commands include: Bypass, Idcode
• Hig h spee d pin-t o -pin de lays of 7. 5 ns
• Ultra-low static power of less than 100
µA
• 100% routa ble with 100% utilizat ion while all pins and
all macrocells are fixed
• Deterministic timing model that is extremely simple to
use
• Up to 20 clo ck s avai la bl e
• Sup port fo r comp lex asynchronous c locking
• Innovative XPLA™ architec tur e combines high sp eed
with extreme flexibility
• 1000 erase/prog ram cycl es guarante ed
• 20 years dat a ret ention guarante ed
• Logic expandable to 37 product terms
•PCI compliant
• Advan ced 0.5
µ E
2
CMOS pr ocess
• Security bit prevents unauthorized access
• D esign entry and verifi cation using industry stan dard
and Xili nx CAE tools
• R eprogram mable usi ng indu stry standard de vice
programmers
• Innovative Control Term structure pr ovides either sum
terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous ma crocel l regi ster pre s et/reset
- U p to tw o as y nc hr o no us clo c ks
• Programm a ble glo bal 3-s t a te pi n f ac il itate s ` be d of
nails' testing without using logic resources
• Available in TQFP and LQFP packages
• Available in both Commercial and Industrial grades
Description
The XCR5128C CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner
®
fami ly o f CPLD s
from Xilinx. These devices combine high speed and zero
pow er in a 12 8 mac r oc ell C PLD . Wi th the F ZP de si gn tec h-
nique, the XCR5128C offers true pin-to-pin speeds of 7.5
ns, w h il e s i m ul tan eo usl y de live r in g po w e r t ha t i s l es s than
100
µA at sta ndb y wi th out th e ne ed for “turbo bits ” or other
power down schemes. By replacing conventional sense
a mpli fier meth ods fo r im plem ent ing pr oduc t te rms (a t ech -
nique that has been used in PLDs since the bipolar era)
with a casca ded ch ain of pure CMOS gates, the dy namic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology and the pat-
ented full CMO S FZP design technique.
The Xilinx FZP CPLDs utilize the patented XPLA
(eXtended Programmable Logic Array) architecture. The
XPLA architecture combi nes the best fe atures of both PLA
and PAL type structures t o deliver high speed and flexible
logic allocation that results in superior ability to make
design changes with fixed pinouts. The XPLA structure in
each logic block provides a fast 7.5 ns PAL path with five
dedi ca te d p rod uct ter ms pe r out p ut. Th is PAL p at h i s j oine d
by an additional PLA structure that deploys a pool of 32
product terms to a fully programmable OR array that can
allocate the PLA product terms to any output in the logic
block. This combination allows logic to be allocated effi-
cientl y throughout the logic block and supports as ma ny as
37 product terms on an out put. The speed with which lo gic
is allocated from the PLA array to an output is only 2ns,
regardless of the number of PLA product terms used, which
results in worst case t
PD
's of o nl y 9 . 5 ns fr om any pin to an y
other pin. In addition, logic that is common to multiple out-
puts can be placed on a single PLA product term and
shared a c ross mul tiple outputs via the OR array, effectively
increasing desi gn density.
The XCR 5128C CPLDs are suppo rted by i nd ustry st andar d
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABE L, VHDL , Veri lo g) an d/ or sch ema t ic ent r y. Des ig n ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
us es Xil inx developed tools incl uding WebFITT ER .
The XCR5128C CPLD is electrically reprogrammable
using industry standard device programmers from vendors
0
XCR5128C: 128 Macrocell
CPLD with Enhanced Clocking
DS 042 (v1 .3) October 9, 2000
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Product Specification
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