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DS025-1

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型号: DS025-1
PDF文件:
  • DS025-1 PDF文件
  • DS025-1 PDF在线浏览
功能描述: Fast, Extended Block RAM, 1.8 V FPGA Family
PDF文件大小: 45.52 Kbytes
PDF页数: 共4页
制造商: XILINX[Xilinx, Inc]
制造商LOGO: XILINX[Xilinx, Inc] LOGO
制造商网址: http://www.xilinx.com
捡单宝DS025-1
PDF页面索引
120%
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-1 (v1.4) April 2, 2001 www.xilinx.com Module 1 of 4
Preliminary Product Specification 1-800-255-7778 1
Features
Fast, Extended Block RAM, 1.8 V FPGA Family
- 560 Kb and 1,120 Kb embedded block RAM
- 130 MHz internal performance (four LUT levels)
- PCI compliant 3.3 V, 32/64-bit, 33/66-MHz
Sophisticated SelectRAM+™ Memory Hierarchy
- 294 Kb of internal configurable distributed RAM
- Up to 1,120 Kb of synchronous internal block RAM
- True Dual-Port™ block RAM
- Memory bandwidth up to 2.24 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to
external memories
· 200 MHz ZBT* SRAMs
· 200 Mb/s DDR SDRAMs
Highly Flexible SelectI O+ Technology
- Supports 20 high-performance interface standards
- Up to 556 singled-ended I/Os or up to 201
diff erential I/O pairs for an aggregate bandwidth of
>100 Gb/s
Complete Industry-Standard Differential Signalling
Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Al I/O signals can be input, output, or bi-directional
- LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink
Technology
- 80 Gb/s chip-to-chip communication link
- Support for Double Data Rate (DDR) interface
- Web-based HDL generation methodology
Eight Fully Digital Delay-Locked Loops (DLLs)
IEEE 1149.1 boundary-scan logic
Supported by Xilinx Foundation Series and Alliance
Series Devel op men t System s
- Inte rnet Team Design (Xili nx iTD) tool ideal for
million-plus gate density designs
- Wide selection of PC or workstation platforms
SRAM-based In-System Configuration
- Unlimited re-programmability
Advanced Packaging Options
- 1.0 mm FG676 and FG900
-1.27mm BG560
0.18
m 6-layer Metal Process with Copper
Interconnect
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
Introduction
The Virtex-E Extended Memory (Virtex-EM) family of
FPGAs is an extension of the highly successful Virtex-E
fa mi ly ar ch itec tu re. The Vi rtex-EM fami ly (devices sh own in
Table 1) includes all of the features of Virtex-E, plus addi-
tional block RAM, useful for applications such as network
switches and high-performance video graphic systems.
Xilinx developed the Virtex-EM product family to enable
cust ome rs t o desig n s yste ms r eq uiring hi gh me mory ban d-
width, such as 160 Gb/s network switches. Unlike traditional
ASIC devices, this family also supports fast time-to-market
delivery, because the development engineering is already
completed. Just complete the design and program the
device. There is no NRE, no silicon production cycles, and no
additional delays for design re-work. In addition, designers
can update the design over a network at any time, providing
prod uc t up grades or upd at es to cu st om ers ev en so on er.
The Virte x-EM family is the result of more than fifteen years
of FPGA design e xperience. Xilinx has a history of support-
ing customer applications by providing the highest level of
logic, RAM, an d features available in the indust ry. The Vir-
tex-EM family, first FPGAs to deploy copper interconnect,
offers the performance and high memory bandwidth for
advanced system integration without the initial investment,
long de velopment cycles, and inventory risk expected in tra-
ditional ASIC development.
0
Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
DS025-1 (v1.4 ) Apri l 2, 2001
00
Preliminary Product Specification
R
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