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CSPPT08-680J

CSPPT08-680J首页预览图
型号: CSPPT08-680J
PDF文件:
  • CSPPT08-680J PDF文件
  • CSPPT08-680J PDF在线浏览
功能描述: CHIP SCALE PARALLEL TERMINATION ARRAY
PDF文件大小: 59.06 Kbytes
PDF页数: 共4页
制造商: CALMIRCO[California Micro Devices Corp]
制造商LOGO: CALMIRCO[California Micro Devices Corp] LOGO
制造商网址: http://www.calmicro.com
捡单宝CSPPT08-680J
PDF页面索引
120%
© 2000 California Micro Devices Corp. All rights reserved.
11/10/2000
1
CSPPT
CALIFORNIA MICRO DEVICES
215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Chip Scale Parallel Termination Array
Features
8,16 or 32 integrated high frequency
bussed terminations
Ultra small footprint Chip Scale Package
Ceramic substrate
0.35mm Eutectic Solder Bumps, 0.65mm pitch
Product Description
The CSPPT is a high performance Integrated Passive
Device (IPD) which provides parallel terminations
suitable for use in high speed bus applications. Eight (8),
sixteen (16), or thirty-two (32) parallel termination
versions are provided. These resistors provide excellent
high frequency performance in excess of 3GHz and are
manufactured to an absolute tolerance as low as ±1%.
Applications
Parallel resistive bus termination
Bussed resistor array
C1290700
SCHEMATIC DIAGRAMS
The Chip Scale Package provides an ultra small
footprint for this IPD and provides minimal parasitics
compared to conventional packaging. Typical bump
inductance is less than 25pH. The large solder bumps
and ceramic substrate allow for standard attachment to
laminate printed circuit boards without the use of
underfill.
CSPPT08
CSPPT16
CSPPT32
R1
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12
4
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3
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C
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C
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67 9
R1
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R1
8
R1
10
R1
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R1 R1
R1 R1
R1
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