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TSZ02201-0R7R0G300040-1-2
TSZ22111
･
15
･
001
8/10
19.DEC.2011 Rev.002
BD52xx series BD53xx series
Datasheet
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
DD
pins reaches the applicable threshold voltage, the V
OUT
terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD52xx series uses an open drain output
type, it is possible to connect a pull-up resistor to V
DD
or another power supply [The output “High” voltage (V
OUT
) in this case
becomes V
DD
or the voltage of the other power supply].
Fig.15 (BD52xxType Internal Block Diagram) Fig.16 (BD53xxType Internal Block Diagram)
Setting of Detector Delay Time
This detector IC can be set delay time at the rise of VDD by the capacitor connected to C
T
terminal.
Delay time at the rise of V
DD
t
PLH
：Time until when Vout rise to 1/2 of V
DD
after V
DD
rise up and beyond the release
voltage(V
DET
+V
DET
)
t
PLH
= -C
CT
×R
CT
×ln
C
CT
: C
T
pin Externally Attached Capacitance R
CT
: C
T
pin Internal Impedance （P. 2 R
CT
refer.）
V
CTH
: C
T
pin Threshold Voltage（P. 2 V CTH refer.） ln : Natural Logarithm
Reference Data of Falling Time (t
PHL
) Output
Examples of Falling Time (t
PHL
) Output
Part Number t
PHL
[µs] -40°C t
PHL
[µs] ,+25°C t
PHL
[µs],+105°C
BD5227 30.8 30 28.8
BD5327 26.8 26 24.8
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveforms
Example: the following shows the relationship between the input voltage VDD, the C
T
Terminal Voltage VCT and the output
voltage
VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Fig.15 and 16).
1
When the power supply is turned on, the output is unsettled from
after over the operating limit voltage (V
OPL) until tPHL. There fore it is
possible that the reset signal is not outputted when the rise time of
V
DD
is faster than tPHL.
2
When VDD is greater than VOPL but less than the reset release
voltage (V
DET+VDET), the C
T
terminal (VCT) and output (VOUT)
voltages will switch to L.
3
If VDD exceeds the reset release voltage (VDET+VDET), then
V
OUT switches from L to H (with a delay to the C
T
terminal).
4
If VDD drops below the detection voltage (VDET) when the power
supply is powered down or when there is a power supply fluctuation,
V
OUT switches to L (with a delay of tPHL).
5
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (V
DET). The
system is designed such that the output does not flip-flop with power
supply fluctuations within this hysteresis width, preventing
malfunctions due to noise
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q1
V
OUT
RESET
R
L
V
DD
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q2
V
OUT
RESET
Q1
V
DD
V
DD
-V
CTH
V
DD
VDD
VDET+ΔVDET
VDET
VOPL
0V
1/2 VDD
tPHL
①
tPLH
tPHL
tPLH
② ③ ④
CT
⑤
VOUT
Fig.17 Timing Waveform
