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83C196MH

83C196MH首页预览图
型号: 83C196MH
PDF文件:
  • 83C196MH PDF文件
  • 83C196MH PDF在线浏览
功能描述: 8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
PDF文件大小: 1547.13 Kbytes
PDF页数: 共41页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝83C196MH
PDF页面索引
120%
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 2004 August 2004 Order Number: 272543-003
®
8XC196MH INDUSTRIAL MOTOR CONTROL
CHM
OS MICROCONTROLLER
The 8XC196MH is a member of Intel’s family of 16-bit MCS
®
96 microcontrollers. It is designed primarily to
con
trol three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
genera
tor specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-
width
modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
co
mplementary non-overlapping PWM pulses with resolutions of 0.125 µs (edge triggered) or 0.250 µs
(cen
tered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can
be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which
contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains
32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and
64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of
– 40°C to + 85°C.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
High Performance CHMOS 16-bit CPU
16 MHz Operating Frequency
32 Kbytes of On-chip OTPROM/ROM
744 Bytes of On-chip Register RAM
Register-to-register Architecture
16 Prioritized Interrupt Sources
Peripheral Transaction Server (PTS) with 15
Pr
ioritized Sources
Up to 52 I/O Lines
3-phase Complementary Waveform Generator
8-channel 8- or 10-bit A/D with Sample and
Hold
2-channel UART
Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
Two Programmable 16-bit Timers with
Qu
adrature Counting Inputs
Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
Flexible 8- or 16-bit External Bus
1.75 µs 16
×
16 Multiply
3 µs 32/16 Divide
Extended Temperature Available
Idle and Powerdown Modes
Watchdog Timer
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