Order Number: 315514-002
Revision 2. 5
82573 Family of GbE Controllers
Datasheet
Product Feature s
PCIe*
— x1 PCIe* interface on ICH7 or MCH devices
— Peak bandwidth: 2 Gb/s per direction
— Power management
— High bandwidth density per pin
MAC
— Optimized transmit and receive queues
— IEEE 802.3x compliant flow control with
software controlled pause times and threshold
values
— Caches up to 64 packet descriptors per queue
— Programmable host memory receive buffers
(256 bytes to 16 KB) and cache line size (16
bytes to 256 bytes)
— 32 KB c onfig urable t ransmit an d receive FIFO
buffer
— Mechanism available for red uci ng interrupts
generated by transmit and receive operation
— Descripto r ri ng managem en t hardw are for
transmit and receive
— Optimized descriptor fetching and write-back
mechanisms
— Wide, pipelined internal data path architecture
PHY
— Integrated PHY for 10/100/1000 Mb/s full and
half duplex operation
— IEEE 802.3ab auto negotiation support
— IEEE 802.3ab PHY compliance and
compatibility
— DSP architectu re implemen ts digital
adaptive equalization, echo cancellation,
and cross-talk cancellation
Host Offloading
— Transmi t and receive IP, TCP and U DP
checksum off-loading capabilities
— Transmit TCP segmentation, IPv6 offloading,
and advanced p a c ket filter ing
— IEEE 802.1q VLAN support with VLAN tag
insertion, stripping and packet filtering for up
to 4096 VLAN tags
— Descripto r ri ng managem en t hardw are for
transmit and receive
Manageability
— Intel® Active Management T echnology (Intel®
AMT) support (82573E only)
— Alerting Standards Format 2.0 and advanced
pass through support (82573E/V only)
— Boot ROM Preboot eXecution Environment
(PXE) Flash interfa ce supp ort
— Compliance with PCI Power Management 1.1
and Advanced Configuration and Power
Interface (ACPI) 2.0 regi s t er s et c o mpliant
— Wa ke on LAN support
Additional
— Three activity and link indication outputs that
directly drive LEDs
— Programmable LEDs
— Internal PLL for clock generation that can use
a 25 MHz crystal
— Power saving feature for the 82573L. During
the L1 and L2 link states, the 82573L asserts
the Clock Request signal (CLKREQ#) to
indicate that its PCIe* reference clock can be
gated
— On-chip po w er c o n t rol circuitry
— Loopback capabilities
— JTAG (IEEE 1149.1) Test Access Port (TAP)
built in silicon
Technology
— Lead-free 196-pin Thin and Fine Pitch Ball Gri d
Array (TF-BGA) pac k age
— Operating temperature: 0° C to 70° C (with
external re gu lators)
— Operating temperature: 0° to 55° C (with on-
die 2.5V regulator)
— Storage temperature -40° C to 125° C
