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March 1996COPYRIGHT
©
INTEL CORPORATION, 1996 Order Number: 290477-004
82375EB/82375SB PCI-EISA BRIDGE (PCEB)
Y
Provides the Bridge Between the PCI
Local Bus and EISA Bus
Y
100% PCI and EISA Compatible
Ð PCI and EISA Master/Slave Interface
Ð Directly Drives 10 PCI Loads and 8
EISA Slots
Ð Supports PCI from 25 to 33 MHz
Y
Data Buffers Improve Performance
Ð Four 32-bit PCI-to-EISA Posted Write
Buffers
Ð Four 16-byte EISA-to-PCI Read/Write
Line Buffers
Ð EISA-to-PCI Read Prefetch
Ð EISA-to-PCI and PCI-to-EISA Write
Posting
Y
Data Buffer Management Ensures Data
Coherency
Ð Flush Posted Write Buffers
Ð Flush or Invalidate Line Buffers
Ð System-Wide Data Buffer Coherency
Control
Y
Burst Transfers on both the PCI and
EISA Buses
Y
32-Bit Data Paths
Y
Integrated EISA Data Swap Buffers
Y
Arbitration for PCI Devices
Ð Supports Six PCI Masters
Ð Fixed, Rotating, or a Combination of
the Two
Ð Supports External PCI Arbiter and
Arbiter Cascading
Y
PCI and EISA Address Decoding and
Mapping
Ð Positive Decode of Main Memory
Areas (MEMCS
Ý
Generation)
Ð Four Programmable PCI Memory
Space Regions
Ð Four Programmable PCI I/O Space
Regions
Y
Programmable Main Memory Address
Decoding
Ð Main Memory Sizes up to
512 MBytes
Ð Access Attributes for 15 Memory
Segments in First 1 MByte of Main
Memory
Ð Programmable Main Memory Hole
Y
Integrated 16-bit BIOS Timer
Y
Only Available as Part of a Supported
Kit
The 82375EB/SB PCI-EISA Bridge (PCEB) provides the master/slave functions on both the PCI Local Bus
and the EISA Bus. Functioning as a bridge between the PCI and EISA buses, the PCEB provides the address
and data paths, bus controls, and bus protocol translation for PCI-to-EISA and EISA-to-PCI transfers. Exten-
sive data buffering in both directions increases system performance by maximizing PCI and EISA Bus efficien-
cy and allowing concurrency on the two buses. The PCEB’s buffer management mechanism ensures data
coherency. The PCEB integrates central bus control functions including a programmable bus arbiter for the
PCI Bus and EISA data swap buffers for the EISA Bus. Integrated system functions include PCI parity genera-
tion, system error reporting, and programmable PCI and EISA memory and I/O address space mapping and
decoding. The PCEB also contains a BIOS Timer that can be used to implement timing loops. The PCEB is
intended to be used with the EISA System Component (ESC) to provide an EISA I/O subsystem interface.
This document describes both the 82375EB and 82375SB components. Unshaded areas describe the
82375EB. Shaded areas, like this one, describe the 82375SB operations that differ from the 82375EB.