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Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
October 1995COPYRIGHT
©
INTEL CORPORATION, 1995 Order Number: 272335-003
87C51/80C51BH/80C31BH
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial/Express
87C51/80C51BH/80C51BHP/80C31BH
*See Table 1 for Proliferation Options
Y
High Performance CHMOS EPROM
Y
24 MHz Operation
Y
Improved Quick-Pulse Programming
Algorithm
Y
3-Level Program Memory Lock
Y
Boolean Processor
Y
128-Byte Data RAM
Y
32 Programmable I/O Lines
Y
Two 16-Bit Timer/Counters
Y
Extended Temperature Range
(
b
40
§
Cto
a
85
§
C)
Y
5 Interrupt Sources
Y
Programmable Serial Port
Y
TTL- and CMOS-Compatible Logic
Levels
Y
64K External Program Memory Space
Y
64K External Data Memory Space
Y
ONCE Mode Facilitates System Testing
Y
Power Control Modes
Ð Idle
Ð Power Down
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In
addition the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on
Intel’s reliable CHMOS III-E technology. Being a member of the MCS
É
51 controller family, the
87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for-
pin compatible with the existing MCS 51 controller family of products.
The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64
byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code
protection and at the same time allows code verification.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH,
unless information applies to a specific device.
