*Otherbrandsandnamesarethepropertyoftheirrespectiveowners.
InformationinthisdocumentisprovidedinconnectionwithIntelproducts.Intelassumesnoliabilitywhatsoever,includinginfringementofanypatentor
copyright,forsaleanduseofIntelproductsexceptasprovidedinIntel’sTermsandConditionsofSaleforsuchproducts.Intelretainstherighttomake
changestothesespecificationsatanytime,withoutnotice.MicrocomputerProductsmayhaveminorvariationstothisspecificationknownaserrata.
June, 2002
COPYRIGHT
©INTELCORPORATION,2002
OrderNumber:272433-005
80C186EB/80C188EBAND80L186EB/80L188EB
16-BITHIGH-INTEGRATIONEMBEDDEDPROCESSORS
X
FullStaticOperation
X
TrueCMOSInputsandOutputs
Y
IntegratedFeatureSet
ÐLow-PowerStaticCPUCore
ÐTwoIndependentUARTseachwith
anIntegralBaudRateGenerator
ÐTwo8-BitMultiplexedI/OPorts
ÐProgrammableInterruptController
ÐThreeProgrammable16-Bit
Timer/Counters
ÐClockGenerator
ÐTenProgrammableChipSelectswith
IntegralWait-StateGenerator
ÐMemoryRefreshControlUnit
ÐSystemLevelTestingSupport(ONCE
Mode)
Y
DirectAddressingCapabilityto1Mbyte
Memoryand64KbyteI/O
Y
SpeedVersionsAvailable(5V):
Ð25MHz(80C186EB25/80C188EB25)
Ð20MHz(80C186EB20/80C188EB20)
Ð13MHz(80C186EB13/80C188EB13)
Y
AvailableinExtendedTemperature
Range(
b
40
§
Cto
a
85
§
C)
Y
SpeedVersionsAvailable(3V):
Ð16MHz(80L186EB16/80L188EB16)
Ð13MHz(80L186EB13/80L188EB13)
Y
Low-Power Operating Modes:
Ð Idle Mode Freezes CPU Clocks but
keeps Peripherals Active
Ð Powerdown Mode Freezes All
Internal Clocks
Y
Supports 80C187 Numeric Coprocessor
Interface (80C186EB PLCC Only)
Y
Available In:
Ð 80-Pin Quad Flat Pack (QFP)
Ð 84-Pin Plastic Leaded Chip Carrier
(PLCC)
Ð 80-Pin Shrink Quad Flat Pack (SQFP)
The 80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are new
to the 80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two independent
Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.
272433–1