© INT EL CORPOR ATIO N, 1997 September, 1997 Order Number: 273123-001
PRELIMINARY
80960MC
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
AND MEMORY MANAGEMENT UNIT
Figure 1. The 80960MC Processor’s Highly Parallel Architecture
Commercial
■ High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Executi on at
25 MHz
■ On-Chip Floating Poi nt Uni t
— Supp ort s IEEE 754 Floating Point
Standard
— Full Transcendental Support
— Fou r 80-Bi t Registers
— 13.6 Million Whetstones/s
(Single Preci sion) at 25 MHz
■ 512-Byte On-Chip Inst ruction Cache
— Direct Mapped
— Parallel Load/ Decode for Uncache d
Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bi t Regi sters
— Fou r Local Reg ist er Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
— Register Scoreboarding
■ On-Chip Memor y Mana gem ent Uni t
— 4 Gbyt e Virtual Addres s Space per
Task
— 4 Kbyte Pages with Superviso r/User
Protection
■ Buil t-in Interrupt Controller
— 32 Priority Levels
— 248 Vectors
— Su pports M8259A
—3.4µs Latency @ 25 MHz
■ Easy to Use, High Bandwid th 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ Multitaski ng and Mul tiprocessor Support
— Autom atic Task dispatching
— Prioriti zed Task Q ueues
■ Advanced Package Technology
— 132-Lead Cerami c Pin Gri d Array
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS CONTROL
LOGIC
32-BIT
BURST
BUS
FOUR
80-BIT FP
REGISTERS
80-BIT
FPU
MMU
