Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
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contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995 September 1995 Order Number: 272596-002
A PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
Figure 1. 80960JD Microprocessor
■
Pin/Code Compatible with all 80960Jx
Processors
■ High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
■ Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
■ Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
■ On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
■ On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
■ High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
■ New Instructions
— Conditional Add, Subtract and Select
— Processor Management
■ High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
■ Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
■ Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
■ Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
PIN 1
132
99
66
33
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A
A80960JD
NG80960JD
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