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January 1995COPYRIGHT
©
INTEL CORPORATION, 1995 Order Number: 271328-001
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
PROCESSOR
#
Socket and Object Code Compatible with 80960CA
#
Two Instructions/Clock Sustained Execution
#
Four 59 Mbytes/s DMA Channels with Data Chaining
#
Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture
Ð Two Instructions/clock Execution
Ð Load/Store Architecture
Ð Sixteen 32-bit Global Registers
Ð Sixteen 32-bit Local Registers
Ð Manipulate 64-bit Bit Fields
Ð 11 Addressing Modes
Ð Full Parallel Fault Model
Ð Supervisor Protection Model
Y
Fast Procedure Call/Return Model
Ð Full Procedure Call in 4 clocks
Y
On-Chip Register Cache
Ð Caches Registers on Call/Ret
Ð Minimum of 6 Frames provided
Ð Up to 15 Programmable Frames
Y
On-Chip Instruction Cache
Ð 4 Kbyte Two-Way Set Associative
Ð 128-bit Path to Instruction Sequencer
Ð Cache-Lock Modes
Ð Cache-Off Mode
Y
On-Chip Data Cache
Ð 1 Kbyte Direct-Mapped,
Write Through
Ð 128 bits per Clock Access on
Cache Hit
Y
Product Grades Available
Ð SE3:
b
40
§
Cto
a
110
§
C
Y
High Bandwidth On-Chip Data RAM
Ð 1 Kbytes On-Chip RAM for Data
Ð Sustain 128 bits per clock access
Y
Four On-Chip DMA Channels
Ð 59 Mbytes/s Fly-by Transfers
Ð 32 Mbytes/s Two-Cycle Transfers
Ð Data Chaining
Ð Data Packing/Unpacking
Ð Programmable Priority Method
Y
32-Bit Demultiplexed Burst Bus
Ð 128-bit Internal Data Paths to
and
from Registers
Ð Burst Bus for DRAM Interfacing
Ð Address Pipelining Option
Ð Fully Programmable Wait States
Ð Supports 8, 16 or 32-bit Bus Widths
Ð Supports Unaligned Accesses
Ð Supervisor Protection Pin
Y
Selectable Big or Little Endian Byte
Ordering
Y
High-Speed Interrupt Controller
Ð Up to 248 External Interrupts
Ð 32 Fully Programmable Priorities
Ð Multi-mode 8-bit Interrupt Port
Ð Four Internal DMA Interrupts
Ð Separate, Non-maskable Interrupt Pin
Ð Context Switch in 750 ns Typical
