• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • 80960CF-25 PDF文件及第1页内容在线浏览

80960CF-25

80960CF-25首页预览图
型号: 80960CF-25
PDF文件:
  • 80960CF-25 PDF文件
  • 80960CF-25 PDF在线浏览
功能描述: 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR
PDF文件大小: 1315.84 Kbytes
PDF页数: 共77页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝80960CF-25
PDF页面索引
120%
© INTEL CORPORATION, 1996 June 1996 Order Number: 272886-001
A PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
• Socket and Object Code Compatible with 80960CA
• Two Instructions/Clock Sustained Execution
• Four 71 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-Bit Burst Bus with Pipelining
32-Bit Parallel Architecture
Two Instructions/clock Execution
Load/Store Architecture
Sixteen 32-Bit Global Registers
Sixteen 32-Bit Local Registers
Manipulates 64-Bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervis or Protection Model
Fast Procedure Call/Return Model
Full Procedure Call in 4 Clocks
On-Chip Register Cache
Caches Registers on Call/Ret
Minimum of 6 Frames Provide d
Up to 15 Programmable Frames
On-Chip Instruction Cache
4 Kbyte Two-W ay Set Associati ve
128-Bit Path to Instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Selectable Big or Little Endian Byte
Ordering
Four On-Chip DMA Channels
71 Mbytes/s Fly-by Transfers
40 Mbytes/s Two-Cycle Transfers
Data Chaining
Data Packing/Unpacking
Programmable Priority Method
32-Bit Demultiplexed Burst Bus
128-Bit Internal Data Paths to
and
from
Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8-, 16- or 32-Bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
High-Speed Interrupt Controller
Up to 248 External Interrupts
32 Fully Programmable Priorities
Multi-mode 8-Bit Interrupt Port
Four Internal DMA Interrupts
Separate, Non-maskable Interrupt Pin
Context Switch in 625 ns Typical
On-Chip Data Cache
1 Kbyte Direct-Mapped, Write Through
128 bits per Clock Acces s on Cache Hit
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价