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80960CA-25

80960CA-25首页预览图
型号: 80960CA-25
PDF文件:
  • 80960CA-25 PDF文件
  • 80960CA-25 PDF在线浏览
功能描述: 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
PDF文件大小: 977.42 Kbytes
PDF页数: 共68页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝80960CA-25
PDF页面索引
120%
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993 November 1993 Order Number: 270727-006
80960CA-33, -25, -16
32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR
Two Instructions/Clock Sustained Execution
• Four 59 Mbytes/s DMA Channels with Data Chaining
• Demultiplexed 32-bit Burst Bus with Pipelining
32-bit Parallel Architecture
Two Instructions/clock Execution
Load/Store Architecture
Sixteen 32-bit Global Registers
Sixteen 32-bit Local Registers
Manipulates 64-bit Bit Fields
11 Addressing Modes
Full Parallel Fault Model
Supervisor Protection Model
Fast Procedure Call/Return Model
Full Procedure Call in 4 Clocks
On-Chip Register Cache
Caches Registers on Call/Ret
Minimum of 6 Frames Provided
Up to 15 Programmable Frames
On-Chip Instruction Cache
1 Kbyte Two-Way Set Associative
128-bit Path to Instruction Sequencer
Cache-Lock Modes
Cache-Off Mode
High Bandwidth On-Chip Data RAM
1 Kbyte On-Chip Data RAM
Sustains 128 bits per Clock Access
Four On-Chip DMA Channels
59 Mbytes/s Fly-by Transfers
32 Mbytes/s Two-Cycle Transfers
Data Chaining
Data Packing/Unpacking
Programmable Priority Method
32-Bit Demultiplexed Burst Bus
128-bit Internal Data Paths to and
from Registers
Burst Bus for DRAM Interfacing
Address Pipelining Option
Fully Programmable Wait States
Supports 8-, 16- or 32-bit Bus Widths
Supports Unaligned Accesses
Supervisor Protection Pin
Selectable Big or Little Endian Byte
Ordering
High-Speed Interrupt Controller
Up to 248 External Interrupts
32 Fully Programmable Priorities
Multi-mode 8-bit Interrupt Port
Four Internal DMA Interrupts
Separate, Non-maskable Interrupt Pin
Context Switch in 750 ns Typical
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