1. General description
The 74AXP1G32 is a single 2-input OR gate.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
This device ensures very low static and dynamic power consumption across the entire
V
CC
range from 0.7 V to 2.75 V. It is fully specified for partial power down applications
using I
OFF
. The I
OFF
circuitry disables the output, preventing the pote nt ially da m ag in g
backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; C
I
= 0.5 pF (typical)
Low output capacitance; C
O
= 1.0 pF (typical)
Low dynamic power consumption; C
PD
= 2.4 pF at V
CC
= 1.2 V (typical)
Low static power consumption; I
CC
= 0.6 A (85 C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C
74AXP1G32
Low-power 2-input OR gate
Rev. 1 — 25 August 2014 Product data sheet
