74AUP1T34-Q100
Low-power dual supply translating buffer
Rev. 2 — 14 January 2019 Product data sheet
1. General description
The 74AUP1T34-Q100 provides a single buffer with two separate supply voltages. Input A is
designed to track V
CC(A)
. Output Y is designed to track V
CC(Y)
. Both, V
CC(A)
and V
CC(Y)
accepts any
supply voltage from 1.1 V to 3.6 V. This feature allows universal low voltage interfacing between
any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times
across the entire V
CC
range from 1.1 V to 3.6 V. This device ensures a very low static and dynamic
power consumption across the entire V
CC
range from 1.1 V to 3.6 V. This device is fully specified
for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the
damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Wide supply voltage range from 1.1 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards:
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
• HBM JESD22-A114F Class 3A. Exceeds 5000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• Wide supply voltage range:
• V
CC(A)
: 1.1 V to 3.6 V
• V
CC(Y)
: 1.1 V to 3.6 V
• Low static power consumption; I
CC
= 0.9 µA (maximum)
• Each port operates over the full 1.1 V to 3.6 V power supply range
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of V
CC
• I
OFF
circuitry provides partial Power-down mode operation
