1. General description
The 74AUP1G374-Q100 provides the single D-type flip-flop with 3-state output. The
flip-flop stores the state of data input (D) that meets the set-up and hold times
requirements on the LOW-to-HIGH CP transition. When pin OE
is LOW, the contents of
the flip-flop is available at the (Q) output. When pin OE
is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE
does not affect the state of the
flip-flop.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power con su mp tio n acro ss th e en tir e V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the ou tp u t, pr eve n tin g the damaging backflow current through
the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V t o 1.95 V )
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low static power consumption; I
CC
= 0.9 A (maximum)
Latch-up pe rform a nc e exceeds 100 mA per JESD 78 Clas s II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
74AUP1G374-Q100
Low-power D-type flip-flop; positive-edge trigger; 3-state
Rev. 1 — 19 February 2013 Product data sheet
