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74AHC74-Q100

74AHC74-Q100首页预览图
型号: 74AHC74-Q100
PDF文件:
  • 74AHC74-Q100 PDF文件
  • 74AHC74-Q100 PDF在线浏览
功能描述: Dual D-type flip-flop with set and reset positive-edge trigger
PDF文件大小: 752.8 Kbytes
PDF页数: 共19页
制造商: NEXPERIA[Nexperia B.V. All rights reserved]
制造商LOGO: NEXPERIA[Nexperia B.V. All rights reserved] LOGO
制造商网址: https://www.nexperia.com/
捡单宝74AHC74-Q100
PDF页面索引
120%
1. General description
The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop
with individual data inputs (D), clock inputs (CP), set inputs (S
D) and reset inputs (RD). It
also has complementary outputs (Q and Q
).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs mu st be st able one set-up time prior to
the LOW to HIGH clock transition for pr edictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages high er tha n V
CC
Input levels:
For 74AHC74-Q100: CMOS level
For 74AHCT74-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74AHC74-Q100;
74AHCT74-Q100
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 2 — 21 April 2015 Product data sheet
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