1. General description
The 74AHC377-Q100; 74AHCT377-Q100 is a high-speed Si-gate CMOS de vice and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A. The 74AHC377-Q100; 74AHCT377-Q100 has eight
edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock
input (CP) loads all flip-flops simultaneously when the data enable input (E
) is LOW. The
state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop. The E
input is only required to
be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher tha n V
CC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
Input levels:
For 74AHC377-Q100: CMOS level
For 74AHCT377-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74AHC377-Q100;
74AHCT377-Q100
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 1 — 3 December 2013 Product data sheet