1. General description
The 74AHC138-Q100 ; 74AHCT138-Q10 0 are high- speed Si-gate CM OS devices and are
pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
with JEDEC standard No. 7A.
The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexer. It
accepts three binary weighted address inputs (A0, A1 and A2). When enabled, it
provides eight mutually exclusive outputs (Y
0to Y7) that are LOW when selected. There
are three enable inputs: two active LOW (E
1andE2) and one active HIGH (E3). Every
output is HIGH unless E
1 and E2 are LOW and E3 is HIGH.
This multiple enable function, allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74AHC138-Q100; 74AHCT138-Q100 devices
and one inverter. The 74AHC138-Q100; 74AHCT138-Q100 can be used as an eight
output demultiplexer by using one of the active LOW enable inputs as the data input and
the remaining enable inputs as strobes. Unused enable inputs must be permanently tied
to their appropriate active HIGH or LOW state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt-trigger action
Demultiplexing capability
Multiple input enab le for ea sy ex pansion
Ideal for memory chip select decoding
Inputs accept voltages higher tha n V
CC
For 74AHC138-Q100 only: operates with CMOS input levels
For 74AHCT138-Q100 only: operates with TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74AHC138-Q100;
74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 2 — 2 April 2014 Product data sheet