1. General description
The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS de vice and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC132-Q100; 74AHCT13 2-Q100 contains four 2-input NAND gates which accept
standard input signals. They can transform slowly changing input signals into sharply
defined, jitter free output signals. The gate switches at different points for positive-going
and negative-going signals. The difference between the positive voltage V
T+
and the
negative V
T
is defined as the hysteresis voltage V
H
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
Inputs accept voltages higher tha n V
CC
Input levels:
For 74AHC132-Q100: CMOS level
For 74AHCT132-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Multiple package options
74AHC132-Q100; 74AHCT132-Q100
Quad 2-input NAND Schmitt trigger
Rev. 1 — 8 November 2013 Product data sheet