Dual 3 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
Data Sheet
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Input voltage: 4.5 V to 20 V
±1% output accuracy
Integrated 90 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 3 A/3 A
Parallel single output: 6 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift, or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductor
External compensation and soft start
Startup into precharged output
Supported by ADIsimPower™ design tool
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load applications
TYPICAL APPLICATION CIRCUIT
INTVCC
R
TOP1
C
C1
R
C1
C
SS1
C
INT
C
DRV
C
IN1
C
BST1
C
BST2
L1
M1
M2
L2
V
IN
V
IN
V
OUT1
C
OUT1
C
OUT2
V
OUT2
R
BOT1
R
TOP2
R
C2
C
C2
C
SS2
C
IN2
R
BOT2
R
OSC
FB1
COMP1
SS1
EN1
PVIN1
BST1
FB2
COMP2
SS2
EN2
PVIN2
BST2
MODE
SCFG
TRK2
TRK1
VDRV
ADP2323
GND
PGOOD2
PGOOD1
SYNC
RT
SW1
DL1
PGND
DL2
SW2
09357-001
Figure 1.
GENERAL DESCRIPTION
The ADP2323 is a full featured, dual output, step-down dc-to-
dc regulator based on current-mode architecture. The ADP2323
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 3 A
outputs or a parallel-to-single 6 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
The switching frequency can be programmed between 250 kHz
and 1.2 MHz, or synchronized to an external clock to minimize
interference in multirail applications. The dual PWM channels
run 180° out of phase, thereby reducing input current ripple as
well as reducing the size of the input capacitor.
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift, providing the possibility for a
stackable multiphase power solution.
The ADP2323 can be set to operate in pulse-frequency modulation
(PFM) mode at a light load for higher efficiency or in forced
PWM for noise sensitive applications. External compensation
and soft start provide design flexibility. Independent enable
inputs and power good outputs provide reliable power sequencing.
To enhance system reliability, the device also includes undervoltage
lockout (UVLO), overvoltage protection (OVP), overcurrent pro-
tection (OCP), and thermal shutdown (TSD).
The ADP2323 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
50
55
60
65
70
75
80
85
90
95
100
0 0.5 1.0 1.5 2.0 2.5 3.0
EFFICIENCY (%)
OUTPUT CURRE NT (A)
V
OUT
= 5V
V
OUT
= 3.3V
09357-002
Figure 2. Efficiency vs. Output Current at V
IN
= 12 V, f
SW
= 600 kHz
