REV. A
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a
AD14060/AD14060L
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1997
Quad-SHARC
®
DSP Multiprocessor Family
FUNCTIONAL BLOCK DIAGRAM
PERFORMANCE FEATURES
ADSP-21060 Core Processor (
...
34)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Twelve 40 Mbyte/s Link Ports (Three per SHARC)
Four 40 Mbit/s Independent Serial Ports (One from
Each SHARC)
One 40 Mbit/s Common Serial Port
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
308-Lead Ceramic Quad Flatpack (CQFP)
2.05" (52 mm) Body Size
Cavity Up or Down, Configurable
Low Profile, 0.160" Height
Hermetic
25 Mil (0.65 mm) Lead Pitch
29 Grams (typical)
u
JC
= 0.368C/W
GENERAL DESCRIPTION
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer.
The AD14060/AD14060L modules have the highest perfor-
mance —density and lowest cost—performance ratios of any in
their class. They are ideal for applications requiring higher levels
of performance and/or functionality per unit area.
The AD14060/AD14060L takes advantage of the built-in multi-
processing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, each SHARC has a direct
link port connection. Externally, each SHARC has a total of
120 Mbytes/s link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
CPA
SPORT 1
TDI
EBOOT,
LBOOT, BMS
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
FLAG
2,0
EMU
CLKIN
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
SHARC_A
(ID
2-0
= 1)
CPA
SPORT 1
EBOOT,
LBOOT, BMS
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
FLAG
2,0
EMU
CLKIN
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDO
SHARC_B
(ID
2-0
= 2)
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
EBOOT,
LBOOT, BMS
EMU
CLKIN
RESET
SPORT 0
TCK, TMS, TRST
FLAG
1
FLAG
3
TDI
SHARC BUS (
ADDR
31-0
,
DATA
47-0,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR
6-1
, RPBA, DMAR
1.2
, DMAG
1.2
)
CPA
SPORT 1
TDO
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
FLAG
2,0
CPA
SPORT 1
SHARC_D
(ID
2-0
= 4)
SHARC_C
(ID
2-0
= 3)
CS
TIMEXP
LINK 1
LINK 3
LINK 4
IRQ
2-0
FLAG
2,0
AD14060/
AD14060L
