REV. A
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a
OP215
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Dual Precision JFET-Input
Operational Amplifier
FEATURES
High Slew Rate: 10 V/s Min
Fast Settling Time: 0.9 s to 0.1% Type
Low Input Offset Voltage Drift: 10 V/C Max
Wide Bandwidth: 3.5 MHz Min
Temperature-Compensated Input Bias Currents
Guaranteed Input Bias Current: 18 nA Max (125C)
Bias Current Specified Warmed Up over Temperature
Low Input Noise Current: 0.01 pA/
÷
Hz Type
High Common-Mode Rejection Ratio 86 dB Min
Pin Compatible with Standard Dual Pinouts
Models with MIL-STD-883 Class B Processing Available
GENERAL DESCRIPTION
The OP215 offers the proven JFET-input performance advantages
of high speed and low input bias current with the tracking and
convenience advantages of a dual op amp configuration.
Low input offset voltages, low input currents, and low drift are
featured in these high-speed amplifiers.
On-chip zener-zap trimming is used to achieve low V
OS,
while a
bias-current compensation scheme gives a low input bias current
V+
NOMINV
INPUT+
V–
J3
J1
Q5
R1
J2
C1
7.4
pF
J4
Q12
–INV
INPUT
Q8
R3
Q6
J5
J11
Q7
NULL
R8
J8 J7
R7
NULL
Q1
Q3
R9
Q11
R4
R5
3.6
k
Q16
Q13
Q15
R6
3.6k
Q14
Q4
Q2
R2
C2
7.4pF
Q10
Q9
J6
Q19
Q17
Q18
Q21
J9
Q20
J10
Q23
R13
Q24
Q22
OUTPUT
R10
Q25
R11
R12
NOTE
R7, R8 ARE ELECTRONICALLY ADJUSTED
ON-CHIP FOR MINIMUM OFFSET VOLTAGE
Figure 1. Simplified Schematic (1/2 OP215)
at elevated temperature. Thus, the OP215 features an input bias
current of 1.4 nA at 70∞C ambient (not junction) temperature
which greatly extends the application usefulness of this device.
Applications include high-speed amplifiers for current output
DACs, active filters, sample-and-hold buffers, and photocell
amplifiers. For additional precision JFET op amps, see the
OP249 and AD712 data sheets.
