1
Data sheet acquired from Harris Semiconductor
SCHS187C
Features
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 13ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C (Data to Output)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are
high-speed Octal Transparent Latches manufactured with
silicon gate CMOS technology. They possess the low power
consumption of standard CMOS integrated circuits, as w ell as
the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch
enable (
LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the
three-state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent of the state of the output enable .
The ’HC533 and ’HCT533 are identical in function to the
’HC563 and CD74HCT563 but have different pinouts. The
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;
the latter are non-inverting types.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC533F3A -55 to 125 20 Ld CERDIP
CD54HC563F3A -55 to 125 20 Ld CERDIP
CD54HCT533F3A -55 to 125 20 Ld CERDIP
CD74HC533E -55 to 125 20 Ld PDIP
CD74HC563E -55 to 125 20 Ld PDIP
CD74HC563M -55 to 125 20 Ld SOIC
CD74HCT533E -55 to 125 20 Ld PDIP
CD74HCT563E -55 to 125 20 Ld PDIP
CD74HCT563M -55 to 125 20 Ld SOIC
January 1998 - Revised July 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54/74HC533, CD54/74HCT533,
CD54/74HC563, CD74HCT563
High-Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed
