SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
D High-Performance Floating-Point Digital
Signal Processor (DSP):
- SM/SMJ320VC33-150
- 13-ns Instruction Cycle Time
- 150 Million Floating-Point Operations
Per Second (MFLOPS)
- 75 Million Instructions Per Second
(MIPS)
D 34K × 32-Bit (1.1-Mbit) On-Chip Words of
Dual-Access Static Random-Access
Memory (SRAM) Configured in 2 × 16K plus
2 × 1K Blocks to improve Internal
Performance
D x5 Phase-Locked Loop (PLL) Clock
Generator
D Very Low Power: < 200 mW @ 150 MFLOPS
D 32-Bit High-Performance CPU
D 16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
D Four Internally Decoded Page Strobes to
Simplify Interface to I/O and Memory
Devices
D Boot-Program Loader
D EDGEMODE Selectable External Interrupts
D 32-Bit Instruction Word, 24-Bit Addresses
D Eight Extended-Precision Registers
D Fabricated Using the 0.18-µm (l
eff
-Effective
Gate Length) TImeline Technology by
Texas Instruments (TI)
D On-Chip Memory-Mapped Peripherals:
- One Serial Port
- Two 32-Bit Timers
- Direct Memory Access (DMA)
Coprocessor for Concurrent I/O and CPU
Operation
D 164-Pin Low-Profile Quad Flatpack (HFG
Suffix)
D 144-Pin Non-hermetic Ceramic Ball Grid
Array (CBGA) (GNM Suffix)
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Two Low-Power Modes
D Two- and Three-Operand Instructions
D Parallel Arithmetic/Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
D Block-Repeat Capability
D Zero-Overhead Loops With Single-Cycle
Branches
D Conditional Calls and Returns
D Interlocked Instructions for
Multiprocessing Support
D Bus-Control Registers Configure
Strobe-Control Wait-State Generation
D 1.8-V (Core) and 3.3-V (I/O) Supply Voltages
description
The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal
CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3x generation of DSPs from Texas
Instruments.
The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TImeline and SM320C3x are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL−PRF−38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
