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型号: 554ADXXXXXXBGR
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功能描述: SiPHY OC-192/STM-64 TRANSMITTER
PDF文件大小: 308.02 Kbytes
PDF页数: 共20页
制造商: SILABS[Silicon Laboratories]
制造商LOGO: SILABS[Silicon Laboratories] LOGO
制造商网址: http://www.silabs.com
捡单宝554ADXXXXXXBGR
PDF页面索引
120%
Preli m inary Rev. 0.31 8/01 Copyright © 2001 by Silicon Laboratories Si5540-DS031
This inform ati on applies to a product under developmen t. Its cha racteristic s and s pecifications are subject to change without notice.
Si5540
SiPHY
OC-192/STM-64 TRANSMITTER
Features
Complete SONET/SDH transmitter for OC-192/STM-64 data rates with integrated
16:1 multiplexer and DSPLL
based clock multiplier unit:
Applications
Description
The Si5540 is a fully integrated low-power transmitter for high-speed serial
communication systems. It combines high speed clock generation with a 16:1
multiplexer to serialize data for OC-192/STM-64 applications. The Si5540 is based
on Silicon Laboratories’ DSPLL
technology which eliminates the external loop
filter components required by traditional clock multiplier units. In addition,
selectable loop filter bandwidths are provided to ensure superior jitter performance
while relaxing the jitter requirements on external clock distribution subsystems.
Support for data streams up to 10.7 Gbps is also provided for applications that
employ forward error correction (FEC).
The Si5540 represents a new standard in low jitter, low power and small size for
10 Gbps serial transmitters. It operates from a single 1.8 V supply over the
industri al t em perature ran ge (–40°C to 85°C).
Functional Block Diagram
Data Rates Supported: OC-192/STM-64,
10Gb E, and 10. 7 Gbps FEC
Low Power Operation 0.6 W (typ)
Small Footprint: 99-Pin BGA Package
(11 x 11 mm)
DSPLL™ Based Clock Multiplier Unit
w/ selectabl e loop filter bandwidths
OIF SFI-4 Compliant Interface
Output Clock Powerdown
Operates with 155 or 622 MHz
Reference Sources
Optional 3.3 V Supply Pin for
LVTTL Compatible Outputs
Singl e 1.8 V Supply Operation
Sonet/ SDH/ATM Rout ers
Add/D rop Mult iplexe rs
Digital Cross Connects
Optical Transceiver M odules
Sonet/ S D H Te s t Equ ipm ent
TXDO U T
TXDIN [15:0]
TXCLK1 6OU T
FIFO RST
FIFOERR
16:1
MUX
FIFO
TXCLK1 6IN
TXM SBSEL
TXCLKO UT
TXSQLCH
2
2
2
R EFC LK
TXLO L
DSPLL
TM
CMU
TXC LKD SBL
2
TXC LK16IN
REFSEL
BW SEL
2
32
16
REFRATE
Bias
Reset
Control
REXT
RES ET
÷
Ordering Information:
Se e p age 17.
Si5364
Bottom View
PRELIMINARY DATA SHEET
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