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530KB622M080BG

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型号: 530KB622M080BG
PDF文件:
  • 530KB622M080BG PDF文件
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功能描述: CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)
PDF文件大小: 183.94 Kbytes
PDF页数: 共10页
制造商: SILABS[Silicon Laboratories]
制造商LOGO: SILABS[Silicon Laboratories] LOGO
制造商网址: http://www.silabs.com
捡单宝530KB622M080BG
PDF页面索引
120%
Preliminary Rev. 0.4 5/06 Copyright © 2006 by Silicon Laboratories Si530/531
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si530/531
CRYSTAL OSCILLATOR (XO)
(10 MH
Z TO 1.4 GHZ )
Features
Applications
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
Networking
SD/HD video
Clock and data recovery
FPGA/ASIC clock generation
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL®
Clock
Synthesis
V
DD
CLK+CLK–
OE
GND
Ordering Information:
See page 6.
Pin Assignments:
See page 5.
(Top View)
Si5602
1
2
3
6
5
4GND
OE
V
DD
CLK+
CLK–
NC
1
2
3
6
5
4GND
NC
V
DD
CLK+
NC
OE
1
2
3
6
5
4GND
NC
V
DD
CLK+
CLK–
OE
Si530 (LVDS/LVPECL/CML)
Si530 (CMOS)
Si531 (LVDS/LVPECL/CML)
PRELIMINARY DATA SHEET
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