October 1995 1/8
ST 486 DX ASIC CORE
Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE
PRELIMINARY DATA
■ Fully S tatic 486 co mpa tible co re able t o
op erate f rom D. C t o 120M H z
■ Manuf act ured in a 0. 35 m icron five layer
metal HCMOS process
■ 8K byte unified instruction and data cache
with write bac k capabilit y
■ Parallel processing in tegral floating point unit,
with automatic power down mode
■ Lo w P ower s y stem mana gem ent m odes
■ Ce ll l ibraries for 2.2V and 3.3V su pply with
5 V I /O interface capabi lity
■ 2 - input NAND delay of 0.160 ns (typ) with
fanout = 2.
■ Broad I/O f uncti onali ty including LVC MO S,
LVTTL, G TL, PE CL, and LV DS.
■ High drive I/ O; capabilit y of sinking up to 48
mA with slew rate control, current sp ike sup-
pression and impedance matching.
■ Generat ors to support S P RAM , DPRA M,
RO M and m any othe r embedded functions.
■ Fully indep endent power and ground confi gu-
rations for inpu ts, core and output s.
■ Program m able I/O ring capability up to 1000
pads.
■ Outpu t buffers capable of driving ISA, EISA ,
PCI , MCA, and SCSI i nterf ace levels.
■ Acti ve pull up and pull down devices.
■ Buskeeper I/O functi ons.
■ Oscillators for wide frequency spectrum.
■ Broad range of 400 SSI cells.
■ Design For Test includes LSSD macr o library
option and IE EE 1149.1 JTA G Bounda ry
Scan archit ecture buil t in.
■ Cadence based d esign system with inter-
faces from multiple workstations.
■ Broad ceram ic and plastic package range.
■ Latchup t rigger curren t > +/ - 500 mA.
ES D protect ion > +/ - 4000 volts.
Sea of G ates
Stand ard C ells
Cust om I/O
Programm able
I/O
e.g RAM DAC
SVGA
CHIPSET / PCI
IDE / IS A
486 D X CO RE
ROM
RAM
DPRAM
Figure 1. Example 486 DX Core ASIC
