Order Number: 306666, Revision: 001
April 2005
Intel St r ataF las h
®
Embedded Memory
(P30)
1-Gbit P30 Family
Datasheet
Product Features
The Intel StrataFlash
®
Embedded Memory (P30) product is the latest generation of Intel
StrataFlash
®
memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device
brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.
Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR
device, and support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options, and three
industry standard package choices.
The P30 product family is manufactured using Intel
®
130 nm ETOX™ VIII process technology.
■ High performance
— 85/88 ns initial access
— 40 MHz with zero wait states, 20 ns clock-to-
data outp ut synchronous-burst read mode
— 25 ns asyn chronous-page read mode
— 4-, 8-, 16- , an d continuous-word burst mo de
— Buffered En hanced Factory Programm ing
(BEFP ) at 5 µs/by te (Typ)
— 1.8 V buffered programming at 7 µs/byte (Typ)
■ Architecture
— Multi- Level Cell Techn ology: High est Density
at Lowes t Cost
— Asymm etrically-blocked archit ecture
— Four 32 -KByte parameter block s: top or
bo ttom confi guratio n
— 128-KByte main blocks
■ Voltage and Power
—V
CC
(core ) voltage: 1.7 V – 2.0 V
—V
CCQ
(I/O) voltag e: 1.7 V – 3.6 V
— Standby cur rent: 55 µA (Typ) for 256-Mbit
— 4-Word sy nchronous read current:
13 mA (Typ) at 40 MHz
■ Quality and Reliability
— Operat ing temperature: –40 °C to +85 °C
• 1-Gbit in SCSP is –30 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VI II process technology (130 nm)
■ Security
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— S electable OTP Space in Main Array:
• 4x32KB parameter blocks + 3x128KB main
bloc ks (top or bottom configurati on)
— A bsolute write protection: V
PP
= V
SS
— P ower-transition erase /program lockout
— I ndividual zero-latency blo ck locking
— Individual block lock-down
■ Software
— 2 0 µs (Typ) program suspend
— 2 0 µs (Typ) erase susp end
—Intel
®
Flash D ata Integrator optimized
— B asic Command Set and Extended Co mmand
Set co mpatible
— C ommon Flash Interface cap able
■ Dens ity and Packaging
— 6 4/128/256-Mbit densities in 56 -Lead TSOP
package
— 6 4/128/256/512-Mbit den sities in 64-Ball
Intel
® Easy BGA pack age
— 6 4/128/256/512-Mbit and 1-Gbit densities in
Intel® QU AD+ SCSP
— 1 6-bit wide data bus
