Order Number: 251902, Revision: 009
April 2005
Intel StrataFlash® Wireless Memory
(L18)
28F640L18, 28F128L18, 28F256L18
Dat ash ee t
Product Features
The Intel StrataFlash
®
wireless memory (L18) device is the latest generation of Intel
StrataFlash
®
memory devices featuring flexible, multiple-partition, dual operati on. It provid es
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables backgr oun d progr ammin g or erasin g to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background. The 8-Mbit or 16-Mbit partitions allow sy stem
designers to choose the size of the code and data segments. The L18 wireless memory device is
manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry-
standard chip scale packaging.
■ High performance Read-While-Write/Erase
— 85 ns initial access
— 54 MHz with z er o w ai t st at e, 14 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16- , and conti nuous- w or d burst m ode
— Burst suspend
— Programmabl e WAIT configuration
— Buffered Enhanced Factory Progra mming
(BEF P) at 5 µs/byte (Typ)
— 1.8 V lo w - power b uffered progr a mming at
7 µs/byte (Typ)
■ Architecture
— Asymmetrically-blocked architecture
— Multi ple 8-Mbit part itions: 64-Mbit and 128-
Mbit devi ces
— Multiple 16-Mb it parti t ions: 256-Mb i t devices
— Four 16-K w o r d param et er bloc ks: top or
bottom c onfigu ra tions
— 64-Kword m ain bl ocks
— Dual- operati on: Read- W hile-Write (RWW) or
Read-While-Erase (RWE)
— Status Regi ster for partition and devi ce status
■ Power
—V
CC
(core) = 1. 7 V - 2. 0 V
—V
CCQ
(I/O) = 1.35 V - 2. 0 V, 1.7 V - 2.0 V
— Standby cu rrent: 30 µA (Typ) for 256-Mbit
— 4-Word synchr onou s rea d curre nt: 15 mA (Typ)
at 54 MH z
— Autom atic Pow er Savi ngs mo de
■ Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 use r-programm able OTP bits
— Absol ut e w rite pro te ct i on: V
PP
= GND
— Power-transition erase/program lockout
— Ind i vidual zero-lat ency block locking
— Indivi dual bl ock lock- down
■ Software
— 20 µs (Typ) program su spen d
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Fla sh I nt er fa ce (CFI) capable
■ Quality and Reliability
— Expanded te m perature : –25° C to +85° C
— Minim um 10 0, 000 eras e cycles per block
— ETOX™ VI I I pr ocess t echnol ogy (0.13 µm)
■ Density and Pa ckaging
— 64-, 128-, an d 256-Mb i t density in V F BGA
packages
— 128/0 and 256/ 0 density in SCSP
— 16-bit w id e data bus
