3 Volt Intel
®
StrataFlash™ Memory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel
®
StrataFlash™ memory produc ts provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliabl e, two-bit-per-cell st orage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
supp ort for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technol og y as Inte l’s one-bit-per-cell products, Intel StrataFlash
memory
devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFl ash component s are ideal for code and da ta applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existi ng Word-Wide FlashFile memor y (28F160S3 and 28F3 20S3), and f irst gene ration
Intel S tr a ta Flash me mo ry ( 28 F640J5 an d 28F320J 5) de vi ce s .
Inte l StrataFlash memory components deliver a new gene ration of fo rward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage o f d e nsity u p grade s and optimize d write c apab ilitie s of future Inte l StrataFl ash m e mory d evices.
Manufa ctured on Inte l
®
0.25 micron ETOX™ VI process technology, Inte l StrataFlash memory pr ovides
the highest levels of quality and reliability.
■ High-Density Symmetrically-Blocked
Architecture
—128 128-Kbyte Erase Blocks (128 M)
—64 128-Kbyte Erase Blocks (64 M)
—32 128-Kbyte Erase Blocks (32 M)
■ High Performance Interface Asynchronous
Page Mode Reads
—110/25 ns Read Access Time (32 M)
—120/25 ns Read Access Time (64 M)
—150/25 ns Read Access Time (128 M)
■ 2.7 V–3.6 V V
CC
Operation
■ 128-bit Pro tection Register
—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
■ Enhanced Data Protection Features
Absolute Protection with V
PEN
= GND
—Flexible Block Locking
—Block Erase/Program Lockout during
Power Transitions
■ Packaging
—56-Lead TSOP Package
—64-Ball Intel
®
Easy BGA Package
■ Cross- C omp a tible Comm and Support Intel
Basic Command Set
—Common Flash Interface
—Scalable Command Set
■ 32-Byte Write Buffer
—6 µs per Byte Effective Programming
Time
■ 12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
—100K Minimum Erase Cycles per Block
■ Automatio n Su spend Options
—Block Erase Suspend to Read
—Block Erase Suspend to Program
—Program Suspend to Read
■ 0.25 µ Intel
®
StrataFlash™ Memory
Technology
Order Number: 290667-008
April 2001
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
