M28C16
16K (2K x 8) PARALLEL EEPROM
with SOFTWARE DATA PROTECTION
NOT FOR NEW DESIGN
November 1997 1/18
This is information on a product still in production but not recommended for new design.
AI01518B
11
A0-A10
W
DQ0-DQ7
V
CC
M28C16
G
E
V
SS
8
RB *
Figure 1. Logic Diagram
A0 - A10 Address Input
DQ0 - DQ7 Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready / Busy
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
FAST ACCESS TIME: 90ns
SINGLE 5V ± 10%SUPPLY VOLTAGE
LOW POWER CONSUMPTION
FAST WRITE CYCLE:
– 64 Bytes Page Write Operation
– Byte or Page Write Cycle: 3ms Max
ENHANCED END OF WRITE DETECTION:
– Data Polling
– ToggleBit
PAGE LOAD TIMER STATUS BIT
HIGH RELIABILITY SINGLE POLYSILICON,
CMOS TECHNOLOGY:
– Endurance >100,000Erase/Write Cycles
– Data Retention >40 Years
JEDEC APPROVED BYTEWIDE PIN OUT
SOFTWARE DATA PROTECTION
M28C16 is replacedby the products
described on the document M28C16A
DESCRIPTION
The M28C16 is a 2K x 8 low power Parallel
EEPROM fabricatedwithSGS-THOMSONproprie-
tary single polysilicon CMOS technology. The de-
vice o ffers fast acce ss time with low po wer
dissipation and requires a 5V power supply. The
circuit has been designed to offer a flexible micro-
controller interface featuring both hardware and
softwarehandshakingwith DataPollingandToggle
Bit. The M28C16 supports 64 byte page write op-
eration. A Software Data Protection (SDP) is also
possibleusing the standard JEDEC algorithm.
24
1
PDIP24 (P) PLCC32 (K)
TSOP28 (N)
8 x13.4mm
24
1
SO24 (MS)
300 mils
Note: * RB function is offered only with TSOP28 package.
