Order Number: 278875-005US
May 2005
Intel® 41210 Serial to Parallel PCI Bridge
Datasheet
Product Features
■ PCI Express Specification, Revision 1.0a
■ Suppor t for single x8, sin gle x4 or single x1
PCI Express oper ation.
■ 64-bit addressing sup port
■ 32-bit CRC (cyclic redundancy checking)
covering all transmitted data packets.
■ 16-bit CRC on all link message
information.
■ Raw b i t-rate on the data pins of 2.5 Gbit/s,
resulting in a raw bandwidth per pin of
250 MB/s.
■ Maximum realized bandwidth on PCI
Express interface is 2 GB/s (in x8 mod e) in
each direction simultaneously, for an
aggregate of 4 GB/s.
■ PCI Local Bus Specification, Revision 2.3.
■ PCI-to-PCI Bridge Specification,
Revision 1.1.
■ PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0b
■ 64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.
■ On Die Termination (ODT) with 8.3KOhm
pull-up to 3.3V f or PCI signals.
■ Six external REQ/GNT Pairs for internal
arbiter on segment A and B respectively.
■ Programmable bus parking on either the
last agent or always on the 41210 Bridge
■ 2-level programmable round-ro bin internal
arbiter with Multi-Transaction Timer
(MTT)
■ External PCI clock-feed support for
asynchronous primary and secondary
domain operation.
■ 64-bi t address i ng for ups tream and
downstream transactions
■ Downstream LOCK# support.
■ No upstream LOCK# support.
■ PCI fast Back-to-Back capable as target.
■ Up to four active and four pending
upstream memory read transactions
■ Up to two downstream delayed (memory
read, I/O read/write and config uration read/
write) transaction.
■ Tunab le inbound read prefetch algorithm
for PCI MRM/MRL commands
■ Device hiding support for secondary PCI
devices.
■ Secondary bus Privat e Memory s uppor t via
Opaque memor y region
■ Local initialization via SMBus
■ Secondary side initialization via Type 0
configuration cycles.
■ Full peer-to-peer read/write capability
between the two secondary PCI segments.
