Intel® 80331 I/O Processor
Datasheet
Product Features
Warning: Intel Corporation products are not intended for use in life support appliances,
devices or syst ems. Use of a Intel products in such applications without written
con s e nt is p ro hib i te d.
■ Integrated Intel XScale
®
core
—500, 667 and 800 MHz
—ARM* V5TE Compliant
—32 KByte, 32-way Set Associative
Instruction Cache with cache locking
—32 KByte, 32-way Set Associative Data
Cache with cache locking. Supports
write through or write back
—2 KByte, 2-way Set Associative
Mini-Data Cache
—128-Entry Branch Target Buffer
—8-Entry Write Buffer
—4-Entry Fill and Pend Buffer
—Performance Monitor Unit
■ Internal Bus 266 MHz/64-b it
—333 MHz on D-0 stepping.
■ PCI-X to PCI-X Bridge
—Primary and Secondary 133MHz/64-bit
PCI-X Interfaces
—8K byte Data Buffers
—Four Secondary PCI Output Clocks
—Secondary Bu s Arbitration
—Private Device and Private Memory
■ Addr e ss Translation Unit
—2 KB or 4 KB Outbound Read Queue
—4 KB Outbou nd Write Qu eue
—4 KB Inbound Read and Write Queue
—Connects Internal Bus to PCI/X Bus A
—Messaging Unit and Expansion ROM
■ Two Programmable 32-bit Timers and
Watchdog Timer
■ Ei ght General Purpose I/O Pins
■ Two I
2
C Bus Interface Units
■ Memory Controller
—PC2700 Double Data Rate (DDR333)
SDRAM
—DDRII 400 SDRAM
—Up to 2 GB of 64-bi t DDR333
—Up to 1 GB of 64-bi t DDRII 400
—Optional Sin gle-bit Error Correction,
Multi-bit Detecti on Support (ECC)
—Supports Unbuffered or Registered
DIMMs and Discrete SDRAM
—32-bit memory support
■ DMA Controller
—Two Independent Channels Connected
to Internal Bus
—Two 1KB Queues in Ch0 and Ch1
—CRC-32C Calculation
■ Application Accelerator UnitRAID 6
support on D-0 stepping
—Performs optional XOR on Read Data
—Compute Parity Across Local Memory
Blocks
—1 KB/512-byte Store Queue
■ Two UART (16550) Units
—64-byte Receive and Transmit FIFOs
—4-pin, Master/Slave Capable
■ Peripheral Bus Interface
—8-/16-bit Data Bus with Two Chip Selects
■ Interrupt Controller Unit
—Four Priority Levels
—Vector Generation
—Tw elve External Interrupt Pins with
High Priority Interrupt (HPI#)
■ 829-Ball, Flip Chip Ball Grid Array (FCBGA)
—37.5 mm
2
and 1.27 mm ball pitch
Document Number: 273943-004US
August 2005