LXT362
Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
Datasheet
The LXT362 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface
and general T1 long and short haul applications. It operates over 22 AWG twisted-pair cables
from 0 to 6 kft and offers Line Buil d Outs and pulse equalization settings for al l T1 Line
Interface Unit (LIU) applications.
LXT362 provides both a serial port for microprocessor control (Host mode) as well as stand-
alone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter
attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS encoding/decoding
and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of
diagnostic loopback modes can also be selected.
Applications
Product Features
■ ISDN Primary Rate Interface (ISDN PRI)
■ CSU/NTU interface to T1 Service
■ Wireless Base Station interface
■ T1 LAN/WAN bridge/routers
■ T1 Mux; Channel Banks
■ Digital Loop Carrier - Subscriber Carrier
Systems
■ Fully integrated transceiver for Long or
Short-Haul T1 interfaces
—Crystal-less digital jitter attenuation
—Select either transmit or receive path
■ No crystal or high speed external clock
required
■ Meets or exceeds specifications in ANSI
T1.102, T1.403 and T1.408; and AT&T
Pub 62411
■ Suppo rts 100 Ω (T1 twisted-pair)
applications
■ Selectable receiver sensitivity – fully
restores the received signal after
transmission through a cable with
attenuation of either 0 to 26 dB, or 0 to
36 dB @ 772 kHz
■ Five Pulse Equalization Settings for T1
sh ort-haul applicati ons
■ Four Line Build-Outs for T1 long-haul
applications from 0 dB to -22.5 dB
■ Transmit/receive performance monitors
with Driver Fail Monitor Open and Loss of
Signal outputs
■ Selectable unipolar or bipolar data I/O and
B8ZS encoding/decoding
■ Line attenuation indication output in 2.9 dB
steps
■ QRSS generat or/d etector for testing or
monitoring
■ Local, remote, and analog loopback, plus
in-band network loopback code generation
and detection
■ Multiple register serial interface for
microprocessor control
■ Available in 28-pin PLCC, 44-pin PQFP,
and 44-pin LQFP packages
As of January 15, 2001, this document replaces the Level One document Order Number: 249033-001
known as LXT362 — Integrated T1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications. January 2001
