21154 PCI-to-PCI Bridge
Datasheet
Pr oduct Features
■ Complies fully with the PCI L o cal Bu s
Specification, Revision 2.1
■ Complies fully with the PCI Po wer
Management Specificat ion, Revision 1.0
1
■ Supports 64-bit extension signals on the
primar y and s ec ondary int erfaces
■ Imple ments d elayed tr ansactions for all PCI
configu ration, I/O, and memory read
co mm an ds–up to thr ee transaction s
si mu lta n eo u sly in ea ch di r ect i on
■ Allows 152 bytes of buffering (data and
address ) for upstream pos ted m emory write
commands and 88 bytes of buffering for
downstream posted memory write
command s—up to nine upstream and five
downstream poste d write trans actions
simultaneously
■ Allows 152 bytes of read data buffering
upstream and 152 bytes of read data
buffering downstream
■ Provi des concurrent primary and secondary
bus operation to isolate traffic
■ Provides ten secondary clock outputs:
—Low skew, permitting direct drive of
option slots
—Indi vidual clock disables, ca pable of
automatic configuration during reset
■ Provides arbitration s upport for nine
secondary bus device s:
—A programmable 2-level arbiter
—Hardware disable control, permitting use
of an external arbi ter
1.
For t he 2115 4–A B and later revisions only. The 21154–AA do es not implement this featu re.
■ Provides a 4-pin general-purpose I/O
interface, access ible through device-
spe cific configurati on space
■ Provides enhanc ed address decoding:
—A 32-bit I/O addre ss range
—A 32-bit memory-mapped I/O addres s
r ange
—A 64-b it prefetchabl e mem ory address
r ange
—I SA-aware mode for legac y support in
the first 64KB of I/O address range
— VGA address ing and VGA palette
snooping support
■ Include s live insertion support
■ Sup ports PCI trans acti on forwarding for th e
f ollowing commands:
—All I/O and memory commands
—Type 1 to Type 1 configuration
commands
—Type 1 to Type 0 configuration
com mands (downstrea m onl y)
—Al l Type 1 to s pecia l cycle confi gura tion
commands
■ Includes downstrea m lo ck s upport
■ Supports both 5- V and 3. 3-V signaling
environments
■ Available in both 33 MHz and 66 Mhz
versions
■ Provides an IEEE standard 1149.1 JTAG
interface
Order N um be r: 27 81 08-00 2
J uly 1999
