Bulletin #1611165
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Bulletin Date: 11/16/2016 Bulletin Effective Date: 11/16/2016
Title: EFM8SB1 Datash ee t update V1. 3
Bulletin Details
Silicon Labs is pleased to announce version 1.3 of the EFM8SB1 datasheet. The release corresponds to
the launch of the EFM8SB1 Automotive grade devices.
Summary of changes:
- The addition of automotive devices in the product selection table and ordering information.
- Addition of AEC-Q100 under the key features and specifications.
- Added a table on SMbus timing and operating frequency in master mode. The table details minimum
and maximum operating frequency for each class, hold times, start times, clock low and clock high
periods, and start and stop conditions.
- Added a brief table on the pins used by the bootlo ade r and a reference to AN945 bootloader application
note.
- Added typical Cyclic Redundancy Check (CRC) Calculation Time for a read or write of a 256 byte block
of flash at 24.5 MHz.
- Added a note linking to the output low voltage and output high voltage table of the port I/Os to the
performance curves.
- Added a section describing the typical connection for debugging EFM8SB1. This includes pin sharing
techniques of the C2 interface; refer to section 5.2 of the datasheet for more information.
- Added Pow er-On Reset Threshold and Power-On Reset Delay specifications for a finite Vdd value and
delay tim es.
- Specified in the UART0 description that it has a single-byte FIFO for transmit and receive.
- Added a note on the sleep power mode that entering sleep mode may disconnect the active debug
session.
- Added a line in the introduction section to mention the reference manual where an individual can find
more technical information on registers and blocks.
EFM8SB1 v1.3 datasheet release
EFM8SB10F8A-A-QFN20
EFM8SB10F8A-A-QFN24
EFM8SB10F8A-A-QFN20R
EFM8SB10F8A-A-QFN24R
EFM8SB10F4G-A-QFN20
EFM8SB10F4G-A-QFN20R
EFM8SB10F8A-A-QFN20
EFM8SB10F8A-A-QFN20R
EFM8SB10F8A-A-QFN24
