Rev. 1.2 4/ 16 Copyright © 2016 by Silicon Laboratories Si3402BISO-EVB
Si3402BISO-EVB
ISOLATED EVALUATION BOARD FOR THE Si3402B
1. Description
The Si3402B isolated evaluation board (Si3402BISO-EVB Rev 2) is a reference design for power supplies in
Power over Ethernet (PoE) Powered Device (PD) applications. The Si3402B is described more completely in the
data sheet and application notes. This document describes only the Si3402BISO-EVB evaluation board. An
evaluation board demo nstrating the non-isolated application is described in the Si3402B-EVB User’s Guide.
2. Planning for Successful Designs
Silicon Labs strongly recommends the use of the schematic and layout databases provided with the evaluation
boards as the starting point for your design. Use of external components other than those described and
recommended in this document is generally discouraged. Refer to Table 2 on page 9 for more information on
critical component specifications. Careful attention to the recommended layout guidelines is required to enable
robust designs and full specification compliance. To help ensure design success, please submit your schematic
and layout databases to www.silabs.com/support for review and feedback.
3. Si3402B Board Interface
Ethernet data and power are applied to the board through the RJ-45 connector (J1). The board itself has no
Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out
to the test points. Power may be applied in the following ways:
Connecting a dc source to Pins 1, 2 and 3, 6 of the Ethernet cable (either polarity).
Connecting a dc source to Pins 4, 5 and 7, 8 of the Ethernet cable (either polarity).
Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS.
The Si3402BISO-EVB board schematics and layout are shown in Figures 1 through 6.
The dc output is at connectors J11(+) and J12(–). Boards are generally shipped configured to produce +5 V output
voltage but can be configured for +3.3 V or other output voltages as shown in Table 2 on page 9. The
preconfigured Class 3 signatur e also can be mo dified ac cord ing to Table 3 on pa ge 10. The D8–D15 Schottky-typ e
diode bridge bypass is recommended only for higher power levels (Class 3 operation). For lower power levels,
such as Class 1 and Class 2, the diodes can be removed. When the Si3402B is used in external diode bridge
configuration, it requires at least one pair of the CTx and SPx pins to be connected to the PoE voltage input
terminals (to the input of the external bridge).
The feedback loop compensation has been optimized for 3.3, 5, 9, and 12 V output as well as with standard and
low ESR cap acitors in the o utput filter section (Table 2 on page 9). The use of low ESR capacitors is recommended
for lower output ripple, improved load transient response an d low temperature (below 0 °C) ope ration.
